1. Technical Field
The present invention relates generally to integrated circuits and more particularly to contacts formed down to active regions under a dielectric layer.
2. Background Art
Integrated circuits are used in most electronic devices such as computers, radios, TV""s, cell phones, etc. The hearts of these integrated circuits are semiconductor devices, which can be transistors, diodes, capacitors, etc. The semiconductor devices are generally formed on semiconductor substrates and are covered by insulating, or dielectric, materials.
For example, transistors are formed by implanting spaced-apart source/drain regions into the semiconductor substrate and forming control gates over the semiconductor substrate above the space between the source/drain regions. A dielectric is then deposited over the transistors. Since electrical connections need to be made to the source/drain regions and to the control gates, metal contacts are formed through the dielectric layer to the tops of the control gates and to the surface of the semiconductor substrate. Since the tops of the control gates and the surface of the semiconductor substrate are at different levels in the dielectric layer, the contacts are referred to as multi-level contacts, and more specifically as two-level contacts.
As the electronics industry seeks greater and greater numbers of semiconductor devices on a single integrated circuit, manufacturers seek better methods to shrink the devices by reducing device geometries or the size of features.
One new technology for shrinking device geometries is called xe2x80x9csilicon-on-insulatorxe2x80x9d or SOI technology. SOI technology deals with the formation of semiconductor devices on a layer of semiconductor material which is over an insulating layer in a semiconductor substrate. A common embodiment of the SOI structure is a single active layer of silicon which overlies a layer of silicon dioxide insulator in a substrate silicon.
In the SOI technology, additional contacts are required to the substrate silicon, which is at a level below the tops of the control gates and the surface of the active layer of silicon. Therefore, SOI technology requires multi-level contacts, which are three-level contacts.
In forming multi-level contacts in SOI technology, an etch process is used with contact holes patterned to have the same diameter. The etch through the dielectric layer reaches the shallowest layer or the top of the gate earlier than the active silicon and much before reaching the deeper substrate silicon. Since the duration of the etch process needs to be sufficient to reach the deepest levels, significant over-etch occurs at the shallowest levels. To reduce over-etch, an underlayer or etch stop layer is provided over the gates, the source/drain regions, and the substrate silicon. The underlayer is either an etch stop dielectric layer or gate material (silicon/metal) and substrate silicon (active and/or SOI substrate).
However, immunity or selectivity of the underlayer to the etch is limited. As a result, a considerable portion of the underlayer is removed during long-duration over-etches. The required thickness of the underlayer is determined by the maximum over-etch and the etch rate of the underlayer, which is related to the selectivity. Multi-level contacts require much more over-etch than a single-level contact.
Unfortunately, the thickness of any underlayer is limited by geometric considerations. This is especially true for the CMOS technologies with very high gate densities. Since contacts to the active silicon are often made between two gates, the thickness of the underlayer needs to be less than one-half of the space between the gate sidewall spacers around the gates where the contact will be formed. If the thickness of the underlayer is greater than one-half the space, the underlayer portions of the two gates will xe2x80x9cmergexe2x80x9d and form an increased thickness of underlayer which will prevent proper etching.
Unfortunately also, if the etch requirement for a given underlayer thickness is above the maximum underlayer thickness allowed by the geometric considerations, then the multi-level contacts cannot be formed with a single etch process. This requires multiple etches and separate patterning for the different level contacts. For example, where two separate patterning steps are required, it will be necessary to mask for the shallow contacts, etch, mask for the deep contacts, and etch. This adds process complexity and cost.
While it is desirable to use a maximum thickness underlayer so as to be able to perform etching with comfortable process margins, this presents a problem. The underlayers usually employed are materials such as silicon nitride and silicon oxynitride, which have dielectric constants higher than the pre-metal dielectric layers. This results in increased parasitic capacitance in such areas as gate-to-contact, gate-fringing, and gate-to-first metal.
In some SOI technologies, no underlayer is used. In these situations, significant over-etch occurs on the active silicon during the multi-level contact etch and in particular down to the substrate silicon. Since selectivity to silicon is limited, this results in etching into the active silicon. Accurate control of the etching is required to avoid shorting out the source/drain regions. This requires greater process control and increased cost.
SOI technology offers the promises of improved device isolation, reduced region and parasitic capacitance, low power and enhanced performance but these problems prevent realization of the promises A solution to solve these problems has been long sought but has long eluded those in the art.
The present invention provides a method for forming an integrated circuit including etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate. The first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings are filled with conductive material. This method results in improved device isolation, reduced region and parasitic capacitance, low power requirements, and enhanced performance as well as less process control requirements and reduced manufacturing costs.
Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.